Active hdl rapidshare

The first method is based on consecutive clicks and the other requires that you hold the mouse button while drawing. Go to the Diagram menu click on the Wire. Move the mouse pointer toward the point where you want to end the wire. When moving the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer. If you want to anchor a corner on the wire being drawn, click with the mouse button.

Click where you want to end the wire. If you want to end the wire in empty diagram space, you must double-click instead of the single click. Move the mouse pointer to the point where you want to start drawing the wire, and then hold down the mouse button.

While holding the mouse button, move the mouse pointer toward the point where you want to end the wire. When you move the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer. To anchor a corner on the wire being drawn, press Space while still holding the mouse button.

Drawing new bus is similar to drawing new wire. The Testbench Wizard is designed for automatic generation of testbench files one macro file and a number of source files based on the user-defined specification. One of the most important information entered by the user is the test vector file name. A testbench generates stimulus for the UUT entity on the basis of test vectors defined in this file.

Select Generate Testbench from the Tools menu. Or from the File tab in the Design Browser , expand the branch showing the contents of the default working library or source file HDL, block or state diagram file. Right-click the entity-architecture pair, module, or cell for which you want to generate a testbench, and then select Generate Testbench from the shortcut menu.

Compilation is a process of analysis of a source file. Analyzed design units contained within the file are placed into the working library in a format understandable to the simulator. When you choose a menu command or toolbar button for compilation, Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. If you want to compile a single file, go to the Files tab in the Design Browser , right-click the file, and choose compile from the shortcut menu.

If you choose Compile All from the Design menu for a given design, the compiler automatically reorders the source files to ensure proper sequence in which design units are compiled see Figure 9. All messages infos, warnings and errors generated during compilation are displayed in the Console window or if enabled, on the Compilation tab.

Library units resulting from the compilation of a source file are placed into the working library selected for this file. By default, all source files in the design will be compiled into the default working library.

Once all needed design units have been successfully compiled, you can initialize simulation. Before you initialize simulation, make sure that:.

Expand a structure of a source file containing a top-level unit or current working library in the Files tab, right-click the desired design unit and then choose Set as Top-Level from the shortcut menu.

Open the Design Setting Window. By default, the General category is displayed. Go to the Top-level category and select a top-level unit from the list of design units.

You have set the desired value of simulation resolution. For this go to Settings from the Design menu. The Design Settings dialog box will open. On the Simulation category, choose either the desire simulation resolution value or Auto.

Click OK to close the dialog and complete the operation see Figure If you run the simulator without any top-level unit selected, Active-HDL will prompt you with a dialog box to select one. To begin simulation, you must choose Initialize Simulation from the Simulation menu.

The command launches elaboration and initialization of the simulation model. During elaboration, the simulator loads design units and builds the simulation model in the computer memory.

During the initialization, all objects in the model signals, variables, etc. You can run simulation for an unspecified amount of time. For that choose Run from the Simulation menu.

At this point you should have a schematic with gates and terminals connected using wires. However, your file in the Design Browser is still preceded by a question mark. When you run the check diagram tool, a DRC report file is created. Open this file by going to the DRC line in the Console and double-click the appropriate line see Figure 27 on the next page.

Figure 27 shows an example of a DRC report file for a schematic with an error and some warnings. To ensure that your design functions as you intend, you need to simulate it. At this point, you are ready to run the simulation using the waveform and stimulators. Similarly, any changes in the file means the file needs to be saved and recompiled prior to restarting the simulation. Figure 41 is an example of a simulation using the steps provided in this tutorial.

Now that you have created a waveform and ran a simulation, you should save that waveform. With the waveform tab active, press Ctrl-s to save, or right-click the tab and select save Figure Remember to use descriptive names. This is the naming convention that will be used in the next assignment. You may have several waveforms for the same design. This is very useful in comparing different signal values and methods of driving the input signals.

However, you should close all waveforms when you are done to avoid confusing signals when simulating other designs see the Important note at the beginning of this section. You should experiment with the different methods available and save the results in separate waveforms for comparison; however, this is optional.

We will walk through a simple, yet common, scenario with a schematic that contains errors and warnings. Some of these problems can be pinpointed and solved by simply running a check diagram and reviewing the DRC. However, the DRC cannot find and report your logic errors. What do you do if you have checked your design, compiled successfully, and when you run your simulation, your results are flawed? The techniques below will show you how to use the tools provided by Active-HDL to trouble-shoot your design, and fix some of the most common mistakes.

Therefore, there are no gate delays. This is a simplified example of what you may encounter in your design process. However, the techniques described above can be applied in the same way to larger, more complicated designs. You need to know how to debug your designs using a simulation as well as the DRC report. Even if you do not run into any problems with this assignment, you may need to use these techniques in the more complex upcoming assignments. Shareware Junction lets you choose from a variety of these products - all in one convenient location.

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